1. Field of the Invention
The present invention relates to electronic integrated circuits. More particularly, the present invention relates to circuits for protecting integrated circuits against damage caused by electrostatic discharge ("ESD").
2. Description of the Prior Art and Related Information
Integrated circuits are susceptible to physical damage and destruction from extremely high voltages and currents induced within them by electrostatic discharge pulses. Such ESD pulses typically originate from handling of the circuit during manufacture, assembly and installation. The susceptibility of integrated circuits to ESD damage becomes even more acute as the density of the integrated circuits becomes greater and the geometry of the devices formed therein becomes smaller. As the device geometries are reduced and the devices are packed more closely together, device breakdown voltages are lowered and currents capable of overheating components are more frequently reached by the voltages and currents induced by an electrostatic discharge event.
Various types of circuits have been used to protect the input and output components of an integrated circuit. In a first type of circuit, a resistor is placed in series in the signal path between the input or output pad and the input or output buffer circuitry, respectively. The resistor serves to reduce current levels, and resulting damage to the IC, during ESD events. Shunting diodes are also sometimes employed in this type of circuit to shunt ESD pulses away from the buffer circuitry. For example, two shunting diodes are commonly employed, one diode having its cathode connected to the positive power supply connection and the second diode having its anode connected to the circuit ground connection. Thus, during an ESD event the voltage level at the diode/pad connection will be limited to a range between one diode voltage drop greater than the power supply voltage and one diode voltage drop below ground. The series resistor also reduces the current coming into this connection so as to prevent damage to the shunting diodes.
In a second type of circuit, shunting metal-oxide semiconductor field-effect transistors ("MOSFETs") having thick gate oxides are coupled between the input or output circuit path to be protected and circuit ground. The MOSFETs' drains and gates are connected to the circuit path to be protected and their sources are connected to circuit ground. The gate oxide thicknesses are chosen to provide threshold voltages for the MOSFETs such that they turn on at predetermined ESD protection voltages, typically approximately .+-.30 volts. MOSFETs of opposite conductivity types are used so as to provide protection against ESD pulses of both polarities. During an ESD event, the MOSFETs turn on rapidly when the ESD induced voltage rises above or below the respective threshold voltages. The turned on MOSFET's conductive channel shunts the ESD induced current to circuit ground and clamps the ESD induced voltage to a safe low level. Once the ESD induced voltage drops below the threshold voltage the MOSFET returns to its off state.
The two above-described types of prior art protection circuits, although somewhat effective, suffer from several drawbacks. In the first type of circuit, the series resistor provides an added load in the input or output circuit. This load may be a significant drawback in high speed integrated circuits or integrated circuits driving high current outputs For example, the load introduced by the resistor acts in conjunction with the input or output capacitance of the other input or output circuitry to produce an "R-C" time constant This R-C time constant becomes critical in many high speed circuits due to the inherent delay, and in analog devices due to signal distortion caused by non-linear group delay. However, if this series resistance were eliminated, the shunting diodes and/or the input/output devices would be destroyed by excessive ESD induced current and the circuit would be unprotected or destroyed.
In the second type of circuit, the typical threshold voltages for thick oxide MOSFETs are higher than the voltages at which modern high speed CMOS devices break down. Thus, by the time the thick oxide MOSFETs turn on, the devices sought to be protected are already destroyed. Lowering the threshold voltage by reducing the thickness of the gate oxide provides no solution, since thinner gate oxides degrade rapidly with ESD currents, causing the device to fail prematurely, thereby destroying the ESD protection device.
Additionally, many specific applications of integrated circuit chips place them in an environment where high voltage DC power sources are present. In such applications, resistance to a sustained DC current resulting from accidental coupling to such a power supply is necessary. The aforementioned ESD protection circuits do not provide protection against such sustained DC currents, however, since both the series resistor and diode shunt circuits would overheat and be destroyed from a sustained high current flow.
Accordingly, there is a need for an on-chip ESD protection circuit which does not introduce signal delay and/or distortion. Moreover, there is a further need for such a circuit which provides ESD protection at the low voltages required by modern VLSI circuits. Additionally, there is a need for an ESD protection circuit which is resistant to damage from coupling to high voltage DC power supplies.